The present invention relates to a technology effective for application to a PLL (Phase-Locked Loop) circuit provided with a plurality of VCO (Voltage-Controlled Oscillators) and capable of performing switching between oscillation frequencies, and a technology effective for application to a PLL circuit used as a local oscillator for generating an oscillation signal having a predetermined frequency, which is merged with a receive signal and a transmit signal in a wireless communication apparatus such as a portable or cellular telephone or the like capable of transmitting and receiving signals lying in plural bands, and to a wireless communication system using the PLL circuit.
As a mobile system like a portable or cellular telephone, may be mentioned, dual-band type cellular telephones capable of handling signals lying in two frequency bands, like, for example, a GSM (Group Special Mobile) using a band which ranges from 880 MHz to 915 MHz and a DCS (Digital Cellular System) using a band which ranges from 1710 MHz to 1785 MHz. In the cellular telephone, a PLL circuit is used as a local oscillator for generating an oscillation signal having a predetermined frequency, which is merged with a receive signal and a transmit signal. However, the cellular telephone capable of handling the signals lying within the two frequency bands much different from each other as described above encounters difficulties in covering the two frequency bands by one VCO from the viewpoint of circuit""s characteristics. Thus, VCO corresponding to their frequencies are provided and selected according to a used frequency band.
FIG. 5 shows an example of a configuration of a conventional PLL circuit employed in a dual-band type cellular telephone. The PLL circuit comprises a divider 11A which frequency-divides a reference frequency signal TCXO like 13 MHz into a signal R (hereinafter called a xe2x80x9creference side pulsexe2x80x9d) of about 200 KHz substantially equal to a channel interval, a divider 11B which frequency-divides a feedback signal F sent from either one of VCO into a pulse N (hereinafter called a xe2x80x9cfeedback side pulsexe2x80x9d) having a frequency of 200 KHz identical to the reference side pulse R, a phase comparator 12 which compares the phase of the feedback side pulse N with that of the reference side pulse R and detects the difference in phase therebetween, a charge pump circuit 13 which delivers an electrical charge corresponding to the detected phase difference and draws or discharges it, a loop filter 14 which generates a voltage corresponding to the electrical charge supplied from the charge pump circuit 13, two voltage-controlled oscillators (VCO) 15A and 15B each of which oscillates at a frequency corresponding to the generated voltage, and a selector switch 16 for selecting and feeding back oscillation outputs of these voltage-controlled oscillators 15A and 15B.
Incidentally, the interval between channels (frequency bands) is 200 KHz in the PLL circuit employed in the cellular telephone. In order to generate a local oscillation signal merged with a transmit/receive signal and identical to each selected channel in frequency from the PLL circuit for the purpose of selecting a desired channel from plural channels, a variable divider capable of changing a division ratio is used as the feedback side divider 11B. When the switching between the channels is performed, the division ratio of the variable divider 11B is changed to another according to a control signal sent from a system controller.
When a used band is changed from a GSM band to a DCS band or from the DCS band to the GSM band, the selection of the division ratio of the variable divider 11B according to the control signal sent from the system controller and the switching between the outputs of the voltage-controlled oscillators (VCO) 15A and 15B by the switch 16 are substantially simultaneously carried out. Since, at this time, the time required to obtain the stabilization of a VCO output owing to the output changeover of the switch 16 is longer than a response time of a division output based on the selection of the division ratio of the variable divider 11B, the switching to the VCO is normally carried out on ahead.
It has however been revealed that the PLL circuit employed in the conventional dual-band type cellular telephone has a problem in that a pull-in time of the PLL circuit becomes long upon band changeover due to the reasons to be described below.
FIG. 6(A) shows the outputs of the dividers 11A and 11B and the output of the charge pump circuit 13 when the PLL circuit has been locked. As shown in the same drawing, the output (reference side pulse R) of the divider 11A and the output (feedback side pulse N) of the variable divider 11B are coincident in phase with each other. The output CP of the charge pump circuit 13 is kept constant at 0 V. When a division ratio n of the variable divider 11B is lowered to decrease the oscillation frequency of the PLL circuit in this state, the cycle of the output (feedback side pulse N) of the variable divider 11B becomes shorter than that of the output (reference side pulse R) of the divider 11A as shown in FIG. 6(B). Therefore, a negative current pulse CP is outputted from the charge pump circuit 13 so as to lower the frequency of each VCO. Since, at this time, the channel interval is 200 KHz within the same band and the division ratio is not greatly varied, the cycle of the feedback F becomes long and hence the PLL circuit is promptly brought to such a locked state as shown in FIG. 6(A).
On the other hand, when the division ratio n of the variable divider 11B is rendered high to increase the oscillation frequency of the PLL circuit, the cycle of the output (feedback side pulse N) of the variable divider 11B becomes longer than that of the output (reference side pulse R) of the divider 11A contrary to the above. Therefore, a positive current pulse CP is outputted from the charge pump circuit 13 so as to increase the frequency of each VCO. Further, the cycle of the feedback signal F becomes short and hence the PLL circuit is promptly brought to the locked state if the channel interval falls within the same band. Thus, the stabilization of the frequency is promptly carried out upon a change in the division ratio n of the variable divider 11B with the selection of the channel within the same band.
Since, however, the changeover in the switch 16 is done upon the changeover of the band from the GSM band to the DCS band, the cycle of the output (feedback side pulse N) of the variable divider 11B becomes abruptly short from a cycle T1 in which a changeover in VCO is done as in the case of a timing t1 shown in FIG. 7. Therefore, a negative current pulse CP long in width is outputted from the charge pump circuit 13 so as to lower the frequency of the corresponding VCO. Further, even if two pulses outputted from the other divider (variable divider B) are introduced during one cycle of the output of one divider (reference side divider 11A herein) as in the case of a cycle T3, the phase comparator 12 does not make a comparison with the two pulses. Therefore, the negative current pulse CP outputted from the charge pump circuit 13 becomes considerably long. As a result, the output of the VCO on the selection side is transferred or transitioned to the lowest frequency of a frequency variable range.
When the division ratio of the variable divider 11B is changed to another with a timing t2 in a cycle T4 upon such a condition, the cycle of the output (feedback side pulse N) of the variable divider 11B becomes long. However, the rising edge of the output (feedback side pulse N) of the variable divider 11B becomes earlier than that of the output (reference side pulse R) of the reference side divider 11A according to the division-ratio switching timing as in the case of a cycle T5. Thus, the negative current pulse CP would be outputted from the charge pump circuit 13 though the positive current pulse CP is expected to be outputted from the charge pump circuit 13. As a result, the PLL circuit is started up from an open state, and phase lock-up, i.e., a frequency pull-in time might be long.
Since the cycle of the output (feedback side pulse N) of the variable divider 11B becomes abruptly long upon the changeover of the band from the DCS band to the GSM band contrary to the above, a positive current pulse CP long in width is outputted from the charge pump circuit 13 so as to increase the frequency of the corresponding VCO. Thus, the output of the VCO on the selection side is transitioned to the highest frequency side in the frequency variable range. When the division ratio of the variable divider 11B is changed to another upon such a condition, the positive current pulse CP is outputted from the charge pump circuit which is originally expected to output the negative current pulse. Thus, the frequency pull-in time of the PLL circuit might be lengthened.
As described above, the conventional PLL circuit has a problem in that whether the initial or first rising edge of the output (feedback side pulse N) of the variable divider 11B becomes earlier or later than the rising edge of the output (reference side pulse R) of the reference side divider 11A after the completion of a division-ratio changeover, is not determined uniquely and depends on each division-ratio switching timing, thus causing a variation in frequency pull-in time. It has been revealed that, in a wireless communication system like a portable or cellular telephone which handles only a voice signal, such a variation in frequency pull-in time at the selection of the VCO and division ratio would not exceed an allowable range. However, when an attempt to add a high-speed communication function to a cellular telephone is made, the amount of the variation in the frequency pull-in time would exceed the allowable range.
An object of the present invention is to reduce a frequency pull-in time at a changeover in VCO in a wireless communication system provided with a PLL circuit having a plurality of VCO.
Another object of the present invention is to allow the completion of frequency pulling-in within a predetermined time upon a changeover in VCO in a wireless communication system provided with a PLL circuit having a plurality of VCO.
The above, other objects and novel features of the invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be explained as follows:
A wireless communication system comprising a PLL circuit having a plurality of oscillators and capable of performing switching between the oscillators to thereby process two or more transmit and receive signals different in frequency band from each other is provided with reset means which resets a voltage applied to each of filter capacitors to a predetermined voltage, based on a signal outputted from control means, when the switching is made between the oscillators.
According to the above means, since each of the oscillators oscillates without being affected by a control voltage prior to its changeover upon the switching between the oscillators, a frequency pull-in time of the PLL circuit can be shortened.
The PLL circuit includes a variable divider which frequency-divides a feedback signal sent from any of the oscillators, which is phase-compared with a frequency signal defined as the reference by the phase comparator. A division ratio of the variable divider is changed based on the signal outputted from the control means to thereby select the frequencies of the transmit and receive signals. Thus, a band for a signal transmitted/received according to the switching between the oscillators can be changed to another, and a desired frequency lying in each band can be selected according to the change in the division ratio of the variable divider.
The resetting of each of the filter capacitors by the reset means can be done so as to reach an arbitrary fixed potential but may preferably be reset to a ground potential. This is because it is the stablest voltage and can easily be obtained.
It is desirable that the change in the division ratio of the variable divider is carried out after the switching between the oscillators has been performed, the variable divider is reset to an initial state after the change in the division ratio, and the resetting of each filter capacitor by the reset means is carried out in interlock with the resetting of the variable divider. This is because since the time required to obtain the stabilization of a frequency after the change in the division ratio of the variable divider is shorter than the time required to obtain the stabilization of a post-change frequency after the switching between the oscillators, a total frequency pull-in time can be shortened.
It is desirable that the change in the division ratio of the variable divider is carried out after the switching between the oscillators has been performed, the resettings of the variable divider and each filter capacitor are started simultaneously after the change in the division ratio of the variable divider, and the resetting of each filter capacitor is released after the variable divider has been released from resetting. Thus, it is possible to avoid that a signal defined as the reference and the edge of a feedback signal are phase-compared immediately after the phase comparator has been released from resetting, thereby preventing a malfunction.
There is provided reset signal generating means which generates a control signal for resetting the variable divider. The reset signal generating means may preferably be configured so as to generate a reset signal brought to an effective level during a period between a first pulse of the frequency signal defined as the reference and a pulse subsequent to the first pulse after the change in division ratio, based on a signal for setting the division ratio of the variable divider and the frequency signal defined as the reference. The timing for resetting the variable divider can be set accurately and easily by generating the rest signal, based on the set signal for the division ratio. Further, the phase of a signal obtained by frequency-dividing a feedback signal with respect to the frequency signal defined as the reference after the release of the resetting can uniquely be determined by generating the reset signal, based on the frequency signal defined as the reference.
It is desirable that during the resetting of the filter capacitors by the reset means, the phase comparator and the charge pump are deactivated or the transfer of the output of the phase comparator to the charge pump is blocked. Thus, the influence of the voltage applied to each filter capacitor due to the output of the charge pump can perfectly be eliminated. It is also possible to avoid the instability of the operation of each oscillator during the reset.
There is provided stop signal generating means which generates a stop signal changed to an effective level in synchronism with a change of a reset control signal to an effective level and changed to an ineffective level during a delay time greater than a pulse width of the frequency signal defined as the reference, rather than a change of the reset control signal to an ineffective level on the basis of the reset control signal generated by the reset signal generating means. The stop signal generating means may preferably be configured so as to control the resetting of each filter capacitor, and the deactivation of the phase comparator and charge pump or the cutting off of the transfer of the output of the phase comparator to the charge pump. Thus, it is possible to avoid that a signal defined as the reference and the edge of a feedback signal are phase-compared immediately after the phase comparator has been released from resetting, thereby preventing a malfunction.